1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory circuit, in particular to an improvement of data retention characteristics.
2. Description of the Related Art
In a non-volatile semiconductor memory cell which stores data by varying a threshold voltage of a transistor through injection of charges into a floating gate, data retention characteristics in a reading mode and a retention mode have been regarded as a problem since an application of a certain voltage, which is smaller than an applied voltage for writing, to the non-volatile memory cell both in the reading mode and the retention mode causes extremely slight writing or erasing.
Also, there occurs a phenomenon that electrons stored in the floating gate escape therefrom not due to an electric field caused by a voltage but due to a thermal energy of the electrons. Continual occurrence of the phenomenon, whose probability is extremely low, may cause a change of a data in ten years, which is thought to be a typical lifetime for consumer products. In order to prevent the change of a data as described above, various means are employed.
For example, there is a method of preventing data from being rewritten by storing data read from a non-volatile memory cell in a latch circuit, and then preventing a current flow through the non-volatile memory cell or applying such a bias as not to generate a voltage difference. In this case, writing and/or erasing of a data by a voltage can be prevented, but there still remains a problem of escape of the stored electrons due to their thermal energy. Accordingly, there is employed a method of making an insulating film thicker to increase energy required for the electrons to escape from the floating gate.
Alternatively, there is a method of changing a bias condition in a retention mode between a non-volatile memory cell in which charges are stored in a floating gate and a cell in which charges are not stored. In this case, retention characteristics of the non-volatile memory cell in which the electrons are stored in the floating gate are improved drastically by injecting the electrons (for example, see JP 2006-331587 A (FIG. 1)).
Further, since a relatively high voltage is necessary for writing of a data, a dedicated device having a high withstanding voltage is required, which is a cause of increase in the number of manufacturing steps, that is, increase in cost therefor. Particularly in a case where a non-volatile memory is used in trimming of an analog value, a memory size of 10 bits is required at most in many cases. Thus, addition of the dedicated device having high withstanding voltage only for the small-size memory is a cause of significant decrease in cost competitiveness of a semiconductor integrated circuit device (for example, see JP 2003-229498 A (FIG. 1)).
In the method of JP 2006-331587 A, an output from the memory is stored in a latch circuit, and an output from the latch circuit is fed back to an input to a memory circuit, thereby improving retention characteristics. However, in this case, the number of elements becomes large, and actual application to the semiconductor integrated circuit device increases a chip size, decreasing cost competitiveness.
In the method of JP 2003-229498 A, a writing select transistor and a reading select transistor are provided in parallel for suppressing fluctuations in a threshold voltage during writing and reducing power consumption during reading. However, a power supply line is the same in reading and writing, and thus the writing and reading select transistors need to be formed of a transistor which can undergo an application of high-voltage during writing. In general, compared with a transistor having lower withstanding voltage, a transistor having higher withstanding voltage shows poor characteristics, and for example, has a smaller drivability and a larger size. When the transistors are formed in a process conforming to the withstanding voltage of the writing select transistor, it is difficult to obtain a transistor having excellent characteristics during reading.